# Copyright (C) 2020 - 2022 Xilinx, Inc.
# Copyright (C) 2023, Advanced Micro Devices, Inc.
# SPDX-License-Identifier: Apache-2.0

RM = rm -rf
VIVADO = $(XILINX_VIVADO)/bin/vivado

VIV_DESIGN = kv260_ispMipiRx_rpiMipiRx_DP

VIV_PRJ_DIR = project
VIV_SCRIPTS_DIR = scripts

VIV_XSA = $(VIV_PRJ_DIR)/$(VIV_DESIGN).xsa
VIV_SRC = $(VIV_SCRIPTS_DIR)/main.tcl

VIV_TIMING_ERROR = "CRITICAL WARNING: \[Timing 38-282\] The design failed to meet the timing requirements"

ISP_DIR= ./ip/isp_single_kv260
ISP_IP = isppipeline.prj 

.PHONY: help
help:
	@echo 'Usage:'
	@echo ''
	@echo '  make xsa'
	@echo '    Generate extensible xsa for platform generation'
	@echo ''

.PHONY: all
all: xsa

$(ISP_IP):
	make -C $(ISP_DIR) ip

xsa: $(VIV_XSA)
$(VIV_XSA): $(VIV_SRC) $(ISP_IP)
	$(VIVADO) -mode batch -notrace -source $(VIV_SRC)
	@grep $(VIV_TIMING_ERROR) vivado.log; if [ $$? = 0 ]; then exit 1; fi

.PHONY: clean
clean:
	$(RM) $(VIV_PRJ_DIR) vivado* .Xil *dynamic* *.log *.xpe
	make -C $(ISP_DIR) clean

